1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the manufacture of CMOS gate structures comprising a predoped gate material, such as a predoped polysilicon, with an improved uniformity of the dopant distribution.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a huge number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operational speed and/or power consumption. In this technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on an appropriate substrate, wherein the ongoing demand for an improved circuit functionality at a maintained chip area or a reduction of chip area while maintaining circuit functionality forces the present trend of scaling transistor dimensions and has additionally rendered transistors with a moderately low ratio of width and length, also referred to herein as narrow width devices, a preferred circuit element for highly advanced CMOS devices. The corresponding reduction of transistor width and length enables a significant reduction of the required chip area of advanced transistor circuit elements, thereby allowing a device functionality and/or chip size that may not be achieved with conventional CMOS devices having a high width/length ratio.
MOS transistors are formed in and on semiconductor regions of a substrate. The regions are separated from adjacent circuit elements by surrounding isolation structures. A typical MOS transistor comprises PN junction regions that are separated from each other by a channel region, which is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The dimension of the channel region corresponding to the distance between the two PN junction regions, which are also referred to as the drain region and the source region, is denoted as channel length and represents the dominant design characteristic of the MOS transistor. The channel width is the dimension of the channel in the substrate plane in the direction perpendicular to the length direction. The channel width is determined by the spacing between the isolation structures in this direction.
By reducing the channel length and width of the transistor, not only the transistor size but also the functional behavior thereof may be specifically designed to obtain a desired transistor performance. The channel length is associated with the gate length and may, in typical MOS transistors, be less than the gate length since the source and drain extension typically extends marginally below the gate electrode. The channel width is substantially identical to the gate width. Presently, a gate length of approximately 0.1 μm and significantly less may be encountered in advanced CMOS devices with corresponding clock frequencies of 2000 MHz and more. A typical gate width of an advanced MOS transistor extends to approximately 0.5 μm or less.
Although the continuous size reduction of transistor elements has provided for significant advantages in view of performance and/or power consumption, a plurality of issues has to be addressed so as to not unduly offset some of the advantages that are offered by the reduced dimensions of the circuit elements. Especially the fabrication of the circuit components having the critical dimensions, such as the gate electrode of the transistor element substantially determining the channel length, requires huge efforts to reliably and reproducibly form these tiny circuit components. For instance, it is an extremely complex process to form gate electrodes having a gate length that is well below the wavelength of the UV radiation used to transfer a layout image from a reticle to a resist layer formed on the substrate. In narrow width transistors, having a substantially reduced channel area, additionally, edge effects at the channel/isolation structure interface, such as edge leakage current and threshold voltage shift, become significant and have to be precisely controlled.
A further difficulty arises from the fact that the PN junctions are defined by dopant profiles that are, at least partially, created by ion implantation and subsequent anneal cycles. Since, typically, reduced feature sizes require higher dopant concentrations to compensate for the reduced conductivity owing to reduced cross-sectional areas, complex implantation cycles are required, wherein the vertical and lateral dopant profile has to be precisely controlled to achieve the desired transistor performance. Since the dopants implanted are subjected to diffusion upon elevated temperatures of the device during the manufacturing processes, very strict requirements have to be met with respect to a thermal budget that describes the diffusivity of the dopants over time. In conventional process technologies, the source/drain implantation is also supplied to the gate electrode acting as an implantation mask during the implant cycles. A reduced transistor gate length also requires extremely shallow PN junctions in order to maintain the required controllability of the channel conductivity. Thus, the doping levels and profiles required in the drain and source regions of advanced transistor elements may necessitate implant processes that may be insufficient to achieve the required conductivity of the polysilicon gate electrode. Moreover, due to the non-uniform dopant distribution of these drain/source implantations, the resulting dopant concentration in the polysilicon gate may not be appropriate for preventing undesired gate charge carrier depletion during transistor operation.
To overcome this problem, a polysilicon predoping process is performed after deposition of the polysilicon gate layer and prior to the gate patterning step. The polysilicon predoping is typically performed by ion implantation and needs to go along with sufficient penetration margin to avoid penetration of dopants through the gate oxide, which otherwise may cause severe radiation damage to the ultra-thin insulation layer. The required penetration margin, however, may result in an undesired dopant distribution in the thickness direction of the polysilicon gate layer. Subsequently performed thermal annealing steps may drive the dopants towards the gate oxide to improve the dopant distribution uniformity but may, for advanced transistors, due to the low thermal budget requirements, not provide the desired distribution uniformity.
Another problem arises from the fact that ion implantation is typically performed by a scanning process. The ion beam impinges approximately perpendicular on the surface of a center region of an aligned substrate, whereas an angle of incidence of the ion beam in an edge region of the substrate in the range of approximately 80-85 degrees may be encountered. The tilted implantation, however, may deteriorate the dopant distribution uniformity in the edge region of the substrate due to shadowing effects caused by, for instance, substrate topography at this stage of manufacture, which may result in an undesired shift of the threshold voltage of transistors formed in the edge region of the substrate.
With reference to FIGS. 1a-1d and 2a-2e, a typical conventional process flow for forming a predoped polysilicon CMOS gate structure for wide width and narrow width (FIG. 2e) transistors will now be described to discuss some of the problems involved in predoping by ion implantation at a center region of a substrate (FIGS. 1a-1d) and at a edge region of a substrate (FIGS. 2a-2e) in more detail. FIGS. 1a-1d and 2b-2e show sectional views of the gate structure in the width direction, i.e., the width direction is in the drawing plane. In FIGS. 1a-1d and 2a-2e, similar or identical components are denoted by the same reference numeral except for the very first digit, which is selected in correspondence with the number of the respective figure.
In FIG. 1a, a CMOS gate structure 100 comprises a substrate 101 comprising N-doped and P-doped crystalline silicon regions 107, 109. A layer of semiconductor gate material 105, which is formed above the silicon regions 107, 109, is separated therefrom by gate insulation layers 113, 115. The layer of semiconductor gate material 105 is typically comprised of polysilicon and the gate insulation layer may be comprised of silicon dioxide, silicon oxynitride and the like. Isolation structures 103 substantially define the dimensions of the N-doped and P-doped crystalline silicon regions 107, 109 and electrically insulate the regions 107, 109 from neighboring circuit elements.
A typical process flow for forming the CMOS gate structure 100 in a center region of a substrate as depicted in FIG. 1a may include the following processes. The substrate 101, typically a silicon substrate, is provided. Thereafter, the isolation structure 103 is formed, for example, of silicon dioxide using well-established photolithography, etch, deposition and polishing techniques. A final wet etch process performed after the polishing step to remove an employed polishing stop layer (not shown) may result in a corresponding substrate topography due to the different etch rates of silicon and silicon oxide. In addition, a well implantation that may comprise several implantation steps with different ion species and different implantation energies is performed to generate a desired well dopant profile in the semiconductor regions 107, 109, for example, a retrograde profile. Thereafter, a thin dielectric layer having the required characteristics for the gate insulation layers 113, 115 may be formed by, for instance, advanced oxidation and/or deposition processes. The polysilicon layer 105 is then formed on the thin dielectric layer by deposition techniques that are well known in the art, for example, by low pressure chemical vapor deposition (LPCVD). The LPCVD process shows a substantially conformal deposition characteristic so that the surface of the deposited polysilicon layer 105 exhibits substantially the topography of the substrate 101 previously structured in the isolation structure forming process.
FIG. 1b schematically shows the CMOS gate structure 100 after the formation of a mask element 111 covering at least the polysilicon layer 105 over the crystalline silicon region 107. The mask element 111 may be formed by patterning a spun-on photoresist layer by means of well-established photolithography and anisotropic etch processes. The patterned resist layer may be formed with an appropriate thickness that provides the required ion blocking effect in the subsequent ion implantation step 120. In the implantation step 120, an N-doped polysilicon region, denoted as 119, is formed by implanting a pentavalent ion species such as, for example, phosphorous or arsenic. In the center region of the substrate 101, the ions impinge on the surface of the substrate 101 substantially perpendicularly to the surface plane. The implant energy is chosen to observe a sufficient penetration margin 118 to avoid penetration of dopants through the gate insulation layer 115. The typical implant energy is on the order of several keV. A thermal annealing step may be performed after the implantation step 120 to drive the dopants towards the gate insulation layer 115 based on the allowed thermal budget with respect to the above-described well profile requirements.
FIG. 1c schematically shows the CMOS gate structure 100 after removal of resist mask element 111 and after the formation of a further mask element 121 covering at least the N-doped polysilicon region 119. The mask element 121 may be formed as noted before with respect to mask element 111. The implantation step 122 may also be performed with an observed penetration margin 116 similar to the implantation step 120 described before but with a trivalent ion species such as, for example, boron or indium, instead of the pentavalent ion species.
FIG. 1d schematically shows the CMOS gate structure 100 after the completion of the implantation step 122 and after the removal of the resist mask element 121. The predoped polysilicon layers 117, 119, exhibiting a non-uniform dopant distribution and being N-doped over the P-doped silicon region 109 and being P-doped over the N-doped silicon region 107, are subjected to a patterning process to form correspondingly doped gate electrodes 177, 179 over the semiconductor regions 107, 109 respectively.
FIGS. 2a-2e illustrate the corresponding implantation process for an edge region of the substrate 201. In FIG. 2a, a side view of the substrate 201 subjected to a scanning implantation process is provided. When the ion beam is deflected to sweep along a line on the substrate, the angle of incidence is varied depending on the distance of the point of incidence from the substrate center. While the ions impinge substantially perpendicular to the surface plane of the substrate at a center region of the substrate, an angle of incidence 204 in the range of 80-85 degrees may be encountered in commercially available implantation tools for edge regions of substrates 201 having a diameter of 200 mm. For 300 and 400 mm substrates, intended for future industrial application, the angle of incidence 204 may be further decreased. The effect of the tilted implantation in the edge region of the substrate on the dopant distribution of the polysilicon layer 205 is illustrated in FIGS. 2b-2e. 
FIG. 2b shows a CMOS gate structure 200 like the CMOS gate structure 100 of FIG. 1b but formed in an edge region of the substrate 201 so that, as noted above, a tilted implantation is performed. Due to shadowing effects, caused by the substrate topography, a region with reduced dopant concentration may be formed in the region 219. The region 219 may even be affected more severely from shadowing effects when the CMOS structure is oriented as shown in FIG. 2b so that the resist mask element 211 is also contributing to the shadowing effect resulting in the shadowed region 210. The region 210 further also indicates the region of lower dopant concentration caused by the above-mentioned implantation margin. It is further to be noted that the dashed line defining the region 210 does not indicate a sharp junction but a gradual transition.
FIG. 2c schematically shows the CMOS gate structure 200 after removal of resist mask element 211 and after the formation of a resist mask element 221. The tilted P-dopant implantation 222 over the N-doped silicon region is again adversely affected by shadowing caused by the substrate topography. In the depicted case, there is no shadowing caused by the resist mask element 221. It is to be mentioned that, for a CMOS gate structure formed with the same orientation on the opposite edge of the substrate 201, the resist mask related shadowing effect may affect the P-doped polysilicon region 217. Furthermore, shadowing in the P-doped polysilicon region 217 may be caused by a resist mask element disposed on an adjacent CMOS gate structure (not shown).
FIG. 2d schematically shows the CMOS gate structure 200 after removal of the resist mask element 221. The predoped polysilicon layers 217, 219 are subjected to a patterning process, as noted before with respect to FIG. 1d, to form correspondingly doped gate electrode structures 277, 279 over the semiconductor regions 207, 209 respectively. In contrast to the dopant distribution of FIG. 1d, the obtained non-uniformity of the dopant distribution in the edge region of the gate electrodes 277, 279 is further increased due to the shadowing effects. Thus, wide width CMOS transistors which may be formed from the CMOS gate structure 200 may exhibit threshold voltage (Vt) shifts affecting the edge of the transistor.
FIG. 2e schematically shows the corresponding CMOS gate structure 200 for narrow width transistors. Due to the reduced width of narrow width transistors, the occurring implantation shadowing effects affect a substantial portion of the predoped polysilicon layers 217, 219. In narrow width transistors, the edge effect may significantly affect the device characteristics of the narrow width transistor, resulting in a non-uniformity of device characteristics of devices formed on different substrate locations, thereby negatively affecting production yield.
In view of the situation identified, there exists a need for an improved technique that enables the further scaling of CMOS transistors, particularly of narrow width transistors, while reducing or avoiding one or more of the problems identified above.